In material processing methodologies, pattern etching involves the application of a thin layer of light-sensitive material, such as photo-resist, to an upper surface of a substrate that is subsequently patterned in order to provide a mask for transferring this pattern to the underlying thin film on a substrate during etching. The patterning of the light-sensitive material generally involves exposure of the light-sensitive material to patterned electromagnetic (EM) radiation using, for example, a photo-lithography system, followed by the removal of the irradiated regions of the light-sensitive material (as in the case of positive photo-resist), or non-irradiated regions (as in the case in negative resist) using a developing solution. Moreover, this mask layer may include multiple sub-layers.
But in attempting to meet the increasing demand to produce smaller features, photo-lithography reaches a limit in resolution, currently at a pitch size of roughly 80 nanometers (nm). So more recently, the use of double patterning and related technologies have become more prevalent to double or otherwise multiply the density or spatial frequency of the pattern. In such frequency multiplying techniques, patterns are applied in two or more lithographic sequences or exposures at a given pitch and interleaved to produce a finer resolution of, for example ½, the given pitch. A resolution of, for example, 60 nm can be produced by interleaving two patterns with a first pattern of 120 nm pitch P overlayed with second pattern, spaced at P/2 from the first. Similarly, such a pattern can be produced by interleaving three patterns of 180 nm pitch spaced from each other at P/3. For convenience, the term “double patterning” is used for a technique involving two or more patterns so interleaved.
Two basic techniques for multiplying the spatial frequency of a pattern have been used, namely: (1) Sidewall spacer process (or sidewall image transfer); and (2) “Double Exposure”, and “Double Patterning”, such as LLE (Litho-Litho-Etch) or LELE (Litho-Etch-Litho-Etch).
In the spacer process, the spacer is used as the final mask to create the final pattern in the thin film. The spacer is generated in a multi-layer mask. The mask layer typically comprises a light-sensitive material, such as a photo-resist layer, that is patterned using conventional photo-lithography techniques. The multi-layer mask may also include a bottom anti-reflective coating (BARC) and/or a hard mask. The pattern in the light-sensitive layer is transferred to the BARC and/or hard mask layers using etching techniques. However, current techniques for removing the light-sensitive layer may damage the BARC, leading to poor profile control and residual film left over before the spacer deposition. In addition, if the BARC does not have the mechanical properties necessary to tolerate the stresses induced during the spacer formation process, then again, poor profile control may result. U.S. Patent Application Publication No. 2009/0311634 A1 entitled “METHOD OF DOUBLE PATTERNING USING SACRIFICIAL STRUCTURE” discusses the problems with the spacer method as well as improved methods of patterning by forming a sacrificial structure over the thin film. U.S. patent application Ser. No. 13/158,899 filed Jun. 13, 2011, and entitled “SIDEWALL IMAGE TRANSFER PITCH DOUBLING AND INLINE CRITICAL DIMENSION SLIMMING”, addresses sidewall image transfer with or without LFLE, also with insertion of a slimming step.
With the Double Patterning techniques, the interleaving of patterns in two or more subsequent exposures is involved. LLE and LELE techniques are examples. With LELE techniques, the substrate cycles between lithographic steps and etching steps (e.g., (a) coat substrate with first resist, (b) image the first resist with first pattern, (c) develop first pattern in the first resist, (d) etch the developed first pattern in the resist into an underlying layer, (e) repeat (a)-(d) for second resist and second pattern). With LLE techniques, all photoresist coating steps and image exposure steps are performed prior to etching (e.g., (a) coat substrate with resist, (b) image the resist with first pattern, (c) image the resist with second pattern, (d) develop the first and second patterns in the resist, and then (e) etch the developed first and second patterns in the resist to underlying layers). L(F)LE (Litho-Freeze-Litho-Etch) is a form of LLE wherein all of the photoresist coating steps and image exposure steps are performed prior to exiting a track system (photoresist spin-coating system) and entering an etching system. The freezing step can involve baking to change the chemical properties of the first pattern material, irradiating the first pattern material with EM radiation to change the chemical properties of the first material pattern, reacting the surface of the first pattern material with a cross-linking material, depositing a protective layer over the first pattern material, or some other method to protect the first pattern during exposure and development of the second pattern. The LLE and L(F)LE processes have the advantage of performing all of the lithographic sequences or exposures prior to removal or transfer of substrates for etching.
With the above described methods, when various layers on a semiconductor substrate are being patterned with multiple patterns during the sequence of steps that leads to the fabrication of a device or structure on the substrate, it is important to accurately and precisely align one pattern relative to another. Identifying and correcting overlay error for multiple patterns is a challenge, particularly as feature sizes become smaller and smaller. Overlay error and its effects are described in a paper by R. S. Ghaida and P. Gupta. Design-Overlay Interactions in Metal Double Patterning. Proc. SPIE 7275, 2009. Overlay error must be detected and measured so that processes can be adjusted to reduce the error to within tolerable limits.
Methods for measuring overlay error include image-based methods and diffraction-based methods applied to test structures printed in a test area arranged within an unused portion of the substrate, such as a scribe line. In the image-based methods, overlay marks may include marks of the box-in-box type to assess the placement of multiple patterns and measure the overlay error. Therein, the implementation of the box-in-box type overlay mark involves printing images with each lithographic step, such as rectangular images of different sizes, for example one inside the other, and then optically measuring their relative positions to produce measurements that identify alignment errors. The image base method has resolution limited by the optical system, that include optics aberration and limited image sensor resolutions. A typical measurement uncertainty is about a couple of nm, that is too larger for contemporary and future nodes.
In the diffraction-based methods, optical scatterometry-based metrology may be applied to a test structure printed in the unused area of the substrate by each of the lithographic steps, wherein light scattered from the printed test structure may be detected and measured. The measurements of scattered light are compared with a library of data to extract the geometry of the measured test structure for comparison with stored measurements of scattered light from reference test structures to determine the existence of various errors. A problem with this method has been the difficulty in obtaining sufficient resolution and sensitivity to identify or distinguish the error being measured.
U.S. Pat. No. 7,467,064, entitled “TRANSFORMING METROLOGY DATA FROM A SEMICONDUCTOR TREATMENT SYSTEM USING MULTIVARIATE ANALYSIS,” describes an integrated metrology tool that utilizes scatterometry for inspecting feature geometry in semiconductor manufacturing. The metrology is increasingly utilized to ensure that individual process steps, as well as a sequence of process steps, adhere to design specifications. In optical scatterometry, periodic gratings are embedded in semiconductor substrates in close proximity to the locations for the formation of operating structures in semiconductor devices. By determining the profile of the periodic grating, the quality of the fabrication process utilized to form the periodic grating, and by extension the operating structure of the semiconductor device proximate the periodic grating, can be evaluated.
In general, optical scatterometry involves illuminating the periodic grating with electromagnetic (EM) radiation, and measuring the resulting diffracted signal. The characteristics of the measured diffraction signal is typically compared to a library of pre-determined diffraction signals (i.e., hypothetical diffraction signals) that are associated with known profiles. When the best match is made between the measured diffraction signal and one of the hypothetical diffraction signals, then the profile associated with the matching hypothetical diffraction signal is presumed to represent the profile of the periodic grating. The process of generating a hypothetical diffraction signal involves performing a large number of complex calculations, which can be time consuming and computationally intensive. Differences in measured signals can often consist merely of a slight shift or small change in the shape of broad spectral features in the measured diffraction signals.
There remains a need to improve the resolution and sensitivity of measurements of overlay error in multiple patterning on semiconductor wafers.